1. Field of the Invention
The invention relates, in general, to NAND flash memory devices and, more particularly, to a method of manufacturing a NAND flash memory device, wherein an electrical interference phenomenon occurring between cells can be reduced by reducing the area of a floating gate.
2. Related Technology
In the manufacture of NAND flash memory, a space in which a unit active region and a unit field region will be formed is decreased in size due to higher integration of devices. For this reason, a dielectric layer and a control gate as well as a floating gate are formed within a narrow active space. Accordingly, an interference phenomenon becomes problematic due to the narrow gap between the gates.
FIG. 1 is a perspective view illustrating a known general method of manufacturing a NAND flash memory device employing Self-Aligned Shallow Trench Isolation (ST-STI). FIG. 1 is shown to describe an electrical interference phenomenon between cells.
Referring to FIG. 1, a tunnel oxide layer 11 and a first polysilicon layer 12 are sequentially formed on a semiconductor substrate 10. The first polysilicon layer 12 and the tunnel oxide layer 11 are selectively etched by an etch process using an isolation mask. The semiconductor substrate 10 is etched using the selectively etched first polysilicon layer 12 as a mask, thus forming trenches.
An insulating layer, such as a High Density Plasma (HDP) oxide layer, is then formed on the entire surface so that the trenches are gap-filled. The insulating layer is polished (for example, by Chemical Mechanical Polishing (CMP)) so that a top surface of the first polysilicon layer 12 is exposed, thus forming isolation layers 13 within the trenches. A second polysilicon layer 14 is formed on the entire surface. The second polysilicon layer 14 is etched using a mask, forming a floating gate including the first polysilicon layer 12 and the second polysilicon layer 14. A dielectric layer 15 and a conductive layer 16 for a control gate are formed on the entire surface.
If the floating gate is formed by the above method, the width of the isolation layer is narrowed due to high device integration. Accordingly, a distance between neighboring floating gate is reduced and, therefore, an interference phenomenon occurs between the neighboring floating gates. The interference phenomenon between the neighboring floating gates is generated because an HDP oxide layer near a tunnel oxide layer serves as a dielectric material. Such a phenomenon can be prevented by etching the top surface of the isolation layer up to a region below the tunnel oxide layer and then gap-filling the polysilicon layer for the control gate up to a region below the tunnel oxide layer.
If the height of the floating gate is reduced, however, the interference phenomenon between the gates is reduced, but the coupling ratio and the program speed of a cell are decreased.
FIG. 2 is a graph illustrating program threshold voltages Vt and interference threshold voltage (Vt) shift values depending on the miniaturization of a device.
In FIG. 2, a curve “a” is a graph indicating an interference threshold voltage (Vt) shift value of a cell depending on each device, and curve “b” is a graph indicating a program threshold voltage (Vt) value depending on each device. From the curves “a” and “b,” it can be seen that as the device shrinks, the interference threshold voltage (Vt) shift value increases but the program threshold voltage (Vt) value decreases, and in the devices of 60 nm or less, both the program threshold voltage (Vt) value and the interference threshold voltage (Vt) shift value exceed a limit value of the devices.